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MU9C1480B-90TAC Datasheet(PDF) 3 Page - MUSIC Semiconductors |
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MU9C1480B-90TAC Datasheet(HTML) 3 Page - MUSIC Semiconductors |
3 / 32 page Pin Descriptions LANCAM B Family Rev. 5.1 3 PIN DESCRIPTIONS Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 25 for more information. Figure 2: 44-Pin LQFP Figure 3: 64-Pin LQFP /E (Chip Enable, Input, TTL) The /E input enables the device while LOW. The falling edge registers the control signals /W, /CM, and /EC. The rising edge locks the daisy chain, turns off the DQ pins, and clocks the Destination and Source Segment counters. The four cycle types enabled by /E are shown in Table 1. /W (Write Enable, Input, TTL) The /W input selects the direction of data flow during a device cycle. /W LOW selects a Write cycle and /W HIGH selects a Read cycle. /CM (Data/Command Select, Input, TTL) The /CM input selects whether the input signals on DQ15–0 are data or commands. /CM LOW selects Command cycles and /CM HIGH selects Data cycles. /EC (Enable Daisy Chain, Input, TTL) The /EC signal performs two functions. The /EC input enables the /MF output to show the results of a comparison, as shown in Figure 9 on page 14. If /EC is LOW at the falling edge of /E in a given cycle, the /MF output is enabled. Otherwise, the /MF output is held HIGH. The /EC signal also enables the /MF–/MI daisy chain, which serves to select the device with the highest-priority match in a string of LANCAMs. Table 4 explains the effect of the /EC signal on a device with or without a match in both Standard and Enhanced modes. /EC must be HIGH during initialization. DQ15–0 (Data Bus, I/O, TTL) The DQ15–0 lines convey data, commands, and status to and from the LANCAM. /W and /CM control the direction and nature of the information that flows to or from the device. When /E is HIGH, DQ15–0 go to HIGH-Z. /MF (Match Flag, Output, TTL) The /MF output goes LOW when one or more valid matches occur during a compare cycle. /MF becomes valid after /E goes HIGH on the cycle that enables the daisy chain (on the first cycle that /EC is registered LOW by the previous falling edge of /E; see Figure 9 on page 14). In a daisy chain, valid match(es) in higher priority devices are passed from the /MI input to /MF. If the daisy chain is enabled but the match flag is disabled in the Control register, the /MF output only depends on the /MI input of the device (/MF=/MI). /MF is HIGH if there is no match or when the daisy chain is disabled (/E goes HIGH when /EC was HIGH on the previous falling edge of /E). The System Match flag is the /MF pin of the last device in the daisy chain. /MF is reset when the active configuration register set is changed. 44-Pin LQFP (Top View) GND DQ4 DQ5 VCC VCC TEST2 GND GND DQ6 DQ7 VCC /MA /MI /MF GND /RESET VCC VCC TEST1 /E /W GND 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 37 38 39 40 41 42 43 44 33 34 35 36 45 46 47 48 NC DQ4 DQ5 VCC VCC TEST2 GND GND DQ6 DQ7 VCC NC GND GND GND NC /MA /MI /MF GND /RESET VCC VCC TEST1 /E /W GND NC NC GND GND NC 64-Pin LQFP (Top View) Table 1: I/O Cycles /W /CM Cycle Type LOW LOW Command Write Cycle LOW HIGH Data Write Cycle HIGH LOW Command Read Cycle HIGH HIGH Data Read Cycle |
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