MEMORY ARRAY

512 X 2048

Package Details

Pin Count

Description

Package Type

32

Package details on pages 8 & 9.

See Page 9 for VX

Pin Functions

A0-A16

Address Inputs

D0-7

Data Input/Output

CS1

Chip Select 1

CS2

Chip Select 2

OE

Output Enable

WE

Write Enable

NC

No Connect

V

CC

Power (+5V)

GND

Ground

128K x 8 SRAM

MSM8128 - 70/85/10/12

Issue 4.5: April 2001

Block Diagram

131,072 x 8 CMOS Static RAM

Features

Access Times of 70/85/100/120 ns

JEDEC standard Dual CS footprints.

Operating Power

550 mW (max)

Low Power Standby (-L)

2.2 mW (max)

Low Voltage Data Retention.

Completely Static Operation

Directly TTL compatible.

May be processed in accordance with MIL-STD-883

Description

The MSM8128 is a 1Mbit monolithic SRAM

organised as 128K x 8. It is currently available

in a VIL Package, with access times of 70, 85,

100, 120ns. It has a low power standby version

and has 3.0V battery backup capability. It is

directly TTL compatible and has common data

inputs and outputs.

Two pinout variants (single and dual CS) are

available.

All versions may be screened in accordance with

MIL-STD-883.

Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear

NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997

Pin Definition

NC

A5

A4

A6

A3

A7

A12

A14

A16

A2

A1

A0

GND

D2

D1

D0

VCC

A9

A11

A8

OE

A13

WE

CS2

A15

A10

CS1

D7

D3

D4

D5

D6

32

26

25

27

24

28

29

30

31

23

22

21

17

18

19

20

1

7

8

6

9

5

4

3

2

10

11

12

16

15

14

13

TOP VIEW

S,V

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PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE