Data Sheet U15700EJ1V0DS

9

(2) Initialization interface signals

(1/2)

Pin Name

I/O

Function

DivMode(2:0)

Division mode

These signals set the division ratio of PClock and SysClock as follows:

111: 5.5

110: 5

101: 4.5

100: 4

011: 3.5

010: 3

001: 2.5

000: 2

Set the input levels of these signals before a power-on reset. Make sure that the levels of these

BigEndian

Input

Endian mode

This signal sets the byte ordering for addressing.

1: Big endian

0: Little endian

Set the input level of this signal before a power-on reset. Make sure that the level of this signal

does not change during VR5500 operation.

BusMode

Input

Bus mode

This signal sets the bus width of the system interface.

1: 64 bits

0: 32 bits

Set the input level of this signal before a power-on reset. Make sure that the level of this signal

does not change during VR5500 operation.

TIntSel

Input

Interrupt source select

This signal sets the interrupt source to be assigned to the IP7 bit of the Cause register.

1: Timer interrupt

0: Int5# input and external write request (SysAD5)

Set the input level of this signal before a power-on reset. Make sure that the level of this signal

does not change during VR5500 operation.

DisDValidO#

Input

ValidOut# delay enable

1: ValidOut# is active even while the address cycle is stalled

0: ValidOut# is active during the address issuance cycle only

Set the input level of this signal before a power-on reset. Make sure that the level of this signal

does not change during VR5500 operation.

DWBTrans#

Input

Doubleword block transfer enable (valid in 32-bit bus mode only)

1: Disabled

0: Enabled

Set the input level of this signal before a power-on reset. Make sure that the level of this signal

does not change during VR5500 operation.

Remark

1: High level, 0: Low level