Issue 5.2 April 2001

PAGE 6

Address

Data Out

Valid Data

t

RC

t

ACS

t

OLZ

t

CLZ(4,5)

t

CHZ(3,4,5)

t

OHZ

t

OH

/CS

/OE

NOTES(READ CYCLE)

1. /WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with /CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

9. /CS=/CS1~4

t

OE

Previous Data Valid

Data Valid

Address

Data Out

t

AA

Read Cycle 1

(Address Controlled, /CS=/OE=V

Read Cycle 2

(/WE = V