Issue 5.0 June 1999

PAGE 7

Valid Data

Address

/OE

/CS

Data In

Data Out

t

WR(5)

High Z

High Z(8)

/WE

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;

write.

6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

11 ./CS=/CS1~4

Write Cycle 1

(/OE = Clock)