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TRSL-7140W Datasheet(PDF) 4 Page - Optoway Technology Inc |
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TRSL-7140W Datasheet(HTML) 4 Page - Optoway Technology Inc |
4 / 5 page Optoway TRSL-7140W / TRSL-7140AW ******************************************************************************************************************************************************************************* ******************************************************************************************************************************************************************************** OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303 Tel: 886-3-5979798 Fax: 886-3-5979737 E-mail: sales@optoway.com.tw http: // www.optoway.com.tw 10/30/2004 V1.0 CONNECTION DIAGRAM PIN Symbol Notes PIN Symbol Notes 1 VpdR Receiver power monitor. This pin must be connected to a positive power supply (Vcc), preferably via a small resistor. Supplier photocurrent and maybe used to monitor receiver power. 11 VccT +3.3V dc transmitter power supply 2 VeeR Receiver ground. 12 VeeT Transmitter ground. 3 VeeR Receiver ground. 13 T Dis Transmitter Disable. Connect this pin to logic “1” to disable module. To enable module connect to logic low “0” 4 NC No connected 14 TD + Transmitter Data In 5 NC No connected 15 TD − Transmitter Data In Bar 6 VeeR Receiver ground. 16 VeeT Transmitter ground. 7 VccR +3.3V dc receiver power supply 17 Bmon − Laser Bias Monitoring – Negative End 8 SD Signal detect. Logic 1 indicate a normal operation. 18 Bmon+ Laser Bias Monitoring – Positive End (Bmon+ - Bmon-) = 10 Ω X laser bias current 9 RD − Receiver Dataout Bar 19 Pmon- Laser Power Monitoring -- Negative end 10 RD+ Receiver Dataout 20 Pmon+ Laser Power Monitoring -- Positive end (Pmon+ - Pmon-) = 200 Ω X monitor photdiode current MS MS Mounting Studs. Connect to Chassis Ground RECOMMENDED CIRCUIT SCHEMATIC TX RX MICROSTRIP6 Z=5OR MICROSTRIP5 Z=50R L2 1uH C2 100nF C4 10uF C3 100nF VCC3.3V L1 1uH C8 10uF C1 100nF MICROSTRIP8 Z=5OR MICROSTRIP7 Z=50R PHY DEVICE TD- TD+ RD+ RD- SD R14 100R Vcc3.3V LVPECL Vcc3.3V LVPECL TO LVTTL STAGE Tdis(LVTTL) Bmon- Bmon+ Pmon+ Pmon- 10nF 200R 3K VCCRX(3.3V) Vpdr Note: 1. TX input is terminated inside the module. 2. Veer and Veet are not internally connected to each other. 3. 50 Ω line pattern and component placements on TD+/TD- and RD+/RD- lines shall be symmetrical for better impedance matching. |
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