Flexible & Versatile PCI Express

Features

PEX 8512 General Features

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12-lane PCI Express switch

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Integrated SerDes

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Up to five ports

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23mm x 23mm, 376-ball PBGA

package

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Typical Power: 2.0 Watts

PEX 8512 Key Features

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Standards Compliant

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PCI Express Base Specification, r1.1

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Standard SHPC Specification, r1.1

(hot-plug)

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High Performance

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Non-blocking internal architecture

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Full line rate on all ports

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Cut-Thru latency: 150ns

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Non-Transparent Bridging

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Configurable Non-Transparent port

for Multi-Host or Intelligent I/O

Support

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Flexible Configuration

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Up to Five configurable ports (x1, x2

and x4)

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Configurable with strapping pins,

EEPROM, I

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0,

L0s, L1, L2/L3 Ready, L2 and L3

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Device states: D0 and D3hot

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Vaux, WAKE#, Beacon support

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Spread Spectrum Clock

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Dual clock domain

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Quality of Service (QoS)

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Two Virtual Channels per port

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Eight Traffic Classes per port

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Fixed and Round-Robin Virtual

Channel Port Arbitration

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Reliability, Availability, Serviceability

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Three Standard Hot-Plug Controllers

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Upstream port as hot-plug client

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Transaction Layer end-to-end CRC

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Poison bit

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Advanced Error Reporting

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Lane Status bits and GPO available

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Per port error diagnostics

• Bad DLLPs

• Bad TLPs

• CRC errors

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JTAG boundary scan

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Fatal Error out-of-band signal option

Multi-purpose, Feature Rich ExpressLane™ PCI Express Switch

The ExpressLane PEX 8512 device offers PCI Express switching capability

enabling users to add scalable high bandwidth, non-blocking interconnection

to a wide variety of applications including servers, storage systems,

communications platforms, blade servers, and embedded-control

products. The PEX 8512 is well suited for fan-out, aggregation, peer-to-

peer, and intelligent I/O module applications.

Highly Flexible Port Configurations

The PEX 8512 offers 12 lanes which can be distributed into three ports or

five ports. In the case of three ports, the ports are configured for symmetric

(each port having the same lane width). The PEX 8512 features a flexible

central packet memory that allocates a memory buffer for each port as

required by the application or endpoint. This buffer allocation along with the

device's flexible packet flow control minimizes bottlenecks when the

upstream and aggregated downstream bandwidths do not match. Any of the

ports can be designated as the upstream port, which can be changed

dynamically.

End-to-end Packet Integrity

The PEX 8512 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require guaranteed error-free packets. These

features are optional in the PCI Express specification, but PLX provides

them across its entire ExpressLane switch product line.

Non-Transparent “Bridging” in a PCI Express Switch

The PEX 8512 supports full non-transparent bridging (NTB) functionality to

allow implementation of multi-host systems and intelligent I/O modules in

applications such as communications, storage, and blade servers. To

ensure quick product migration, the non-transparency features are

implemented in the same fashion as in standard PCI applications.

Non-transparent bridges allow systems to isolate memory domains by

presenting the processor subsystem as an endpoint, rather than another

memory system. Base address registers are used to translate addresses;

doorbell registers are used to send interrupts between the address domains;

and scratchpad registers are accessible from both address domains to allow

inter-processor communication.

Two Virtual Channels

The ExpressLane PEX 8512 switch supports two Virtual Channels (VCs) and

eight Traffic Classes (TCs). The mapping of Traffic Classes to port-specific

Virtual Channels allows for different mappings for different ports. In

addition, the devices offer user-selectable Virtual Channel arbitration

algorithms to enable users to fine tune the Quality of Service (QoS) required

for a specific application.

PEX 8512

Version 1.2 2007