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P89CV51RC2FA Datasheet(PDF) 11 Page - NXP Semiconductors |
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P89CV51RC2FA Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 73 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx [1] Unimplemented bits in SFRs (labeled ‘-’) are ‘X’ (unknown) at all times. Unless otherwise specified, 1s should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are 0s although they are unknown when read. Bit address 87 86 85 84 83 82 81 80 SPCR SPI Control Register D5H SPIE SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPSR SPI Status Register AAH SPIF WCOL - - ---- SPDAT SPI Data 86H -------- SP Stack Pointer 81H -------- Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer/counter Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit address CF CE CD CC CB CA C9 C8 T2CON* Timer/counter 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD Timer 2 Mode control C9H ------ T2OE DCEN TH0 Timer 0 High 8CH -------- TH1 Timer 1 High 8DH -------- TH2 Timer 2 High CDH -------- TL0 Timer 0 Low 8AH -------- TL1 Timer 1 Low 8BH -------- TL2 Timer 2 Low CCH -------- TMOD Timer/counter 0 and 1 Mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 WDTRST WatchDog Timer Reset A6H -------- Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR address Bit functions and addresses[1] MSB LSB |
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