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PIC18F8620 Datasheet(PDF) 8 Page - Microchip Technology |
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PIC18F8620 Datasheet(HTML) 8 Page - Microchip Technology |
8 / 12 page PIC18F8720/8620/6720/6620 DS80172C-page 8 © 2005 Microchip Technology Inc. 7. Module: Instruction Set (BTG) In Table 24-1: PIC18FXXXX Instruction Set (page 262), the BTG instruction has been changed (change shown in bold text). 8. Module: OSCCON Register In the OSCCON register (Register 2-1, page 25), the Reset value for the SCS bit (OSCCON<0>) was incorrectly stated as R/W-1 and has been changed to R/W-0. 9. Module: A/D Converter Characteristics In Table 26-25: A/D Converter Characteristics (page 340), specification A40 and Note 6 have been added: TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXXXX (INDUSTRIAL, EXTENDED) PIC18LFXX20 (INDUSTRIAL) TABLE 24-1: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb BIT-ORIENTED FILE REGISTER OPERATIONS BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Param No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bit A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.0V A05 EG Gain Error — — <±1 LSb VREF = VDD = 5.0V A06 EOFF Offset Error — — <±1.5 LSb VREF = VDD = 5.0V A10 — Monotonicity guaranteed(2) —VSS ≤ VAIN ≤ VREF A20 A20A VREF Reference Voltage (VREFH – VREFL) 1.8V 3V — — — — V V VDD < 3.0V VDD ≥ 3.0V A21 VREFH Reference Voltage High AVSS —AVDD + 0.3V V A22 VREFL Reference Voltage Low AVSS – 0.3V(5) —VREFH V A25 VAIN Analog Input Voltage AVSS – 0.3V(5) —AVDD + 0.3V(5) VVDD ≥ 2.5V (Note 3) A30 ZAIN Recommended Impedance of Analog Voltage Source —— 2.5 k Ω (Note 4) A40 IAD A/D Current from VDD PIC18FXXXX — 180 — μA Average current during conversion. PIC18LFXX20 — 90 — μA A50 IREF VREF Input Current (Note 1) — — — — 5 150 μA μA During VAIN acquisition. During A/D conversion cycle. Note 1: Vss ≤ VAIN ≤ VREF 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: For VDD < 2.5V, VAIN should be limited to <.5 VDD. 4: Maximum allowed impedance for analog voltage source is 10 k Ω. This requires higher acquisition times. 5: IVDD – AVDDI must be <3.0V and IAVSS – VSSI must be <0.3V. |
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