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SM8951AL25 Datasheet(PDF) 5 Page - SyncMOS Technologies,Inc |
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SM8951AL25 Datasheet(HTML) 5 Page - SyncMOS Technologies,Inc |
5 / 16 page SyncMOS Technologies International, Inc. SM8951A/8952A 8-Bits Micro-controller With 4/8KB flash embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.1 SM8951A/8952A 08/2006 5 SFR Memory Map $F8 $FF $F0 B $F7 $E8 $EF $E0 ACC $E7 $D8 $DF $D0 PSW $D7 $C8 T2CON RC2L RC2H TL2 TH2 $CF $C0 $C7 $B8 IP SCONF $BF $B0 P3 $B7 $A8 IE $AF $A0 P2 $A7 $98 SCON SBUF WDTC $9F $90 P1 $97 $88 TCON TMOD TL0 TL1 TH0 TH1 $8F $80 P0 SP DPL DPH PCON $87 Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A Extension Function Description Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. The SM8951/8952 WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8958A been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. |
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