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74HC240PW Datasheet(PDF) 4 Page - NXP Semiconductors |
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74HC240PW Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 18 page 74HC_HCT240_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 2 August 2007 4 of 18 NXP Semiconductors 74HC240; 74HCT240 Octal buffer/line driver; 3-state; inverting 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values [1] For DIP20 packages: above 70 °C, P tot derates linearly with 12 mW/K. For SO20 packages: above 70 °C, P tot derates linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C, P tot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C, Ptot derates linearly with 4.5 mW/K. 2A0 17 data input 1Y0 18 bus output 2OE 19 output enable input (active LOW) VCC 20 supply voltage Table 2. Pin description …continued Symbol Pin Description Table 3. Function table[1] Input Output nOE nAn nYn LLH LH L HX Z Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7 V IIK input clamping current VI < −0.5 V or VI >VCC + 0.5 V - ±20 mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V - ±20 mA IO output current −0.5 V < VO < VCC + 0.5 V - ±35 mA ICC supply current - 70 mA IGND ground current −70 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation [1] DIP20 package - 750 mW SO20, SSOP20, TSSOP20 and DHVQFN20 packages - 500 mW |
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