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DS26556 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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DS26556 Datasheet(HTML) 11 Page - Maxim Integrated Products |
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11 / 368 page  DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver 11 of 368 NRZ format option Transmitter power-down Transmitter 50mA short-circuit limiter with current-limit-exceeded indication Transmit open-circuit-detected indication 2.1.3 Clock Synthesizer Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from recovered receive clock 2.1.4 HDLC Controllers HDLC Engine (One per Framer): Independent 64-byte Rx and Tx Buffers with Interrupt Support Access FDL, Sa, or Single DS0 Channel Compatible with Polled or Interrupt Driven Environments 2.1.5 Test and Diagnostics Full-Featured BERTs • Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (x n + xy + 1) and seed are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2 n - 1). • Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n = 1 – 32 and pattern = 0 – 2 n - 1). • 24-bit error count and 32-bit bit count registers • Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific rate. The rate 1/10 n is programmable (n = 1 to 7). • Pattern synchronization at a 10 -3 BER – Pattern synchronization will be achieved even in the presence of a random Bit Error Rate (BER) of 10 -3. BPV Insertion F-Bit Corruption for Line Testing Loopbacks Remote Local Per-Channel IEEE 1149.1 Support 2.2 Cell/Packet Interface 2.2.1 General • Programmable system interface type – When performing cell mapping/demapping, the system interface can be programmed as a UTOPIA Level 2 Bus or a UTOPIA Level 3 Bus or a POS-PHY Level 2 or Level 3 Bus. When performing packet mapping/demapping, the system interface can be programmed as a POS-PHY Level 2 Bus or a POS-PHY Level 3 Bus. • Selectable system interface bus width – The data bus can be a 16-bit or 8-bit bus. • Supports clock speeds up to 52 MHz. • Supports multiple ports on the system interface – Each line has its own port address for access via the system interface. • Programmable system interface port address – The address assigned to each system interface port is programmable to allow multiple devices to operate on the same bus. • Supports per port system loopback – Each port has can be placed in system loopback which causes cells/packets from the transmit FIFO to looped back to the receive FIFO. • System interface bit/byte reordering – In 16-bit mode the order of the bytes as transferred across the system interface is programmable, i.e., the first byte received/transmitted can be transferred in ([15:8]) or [7:0]. The order of the bits as transferred across the system interface is programmable on a per port basis, i.e., the first bit received/transmitted can be transferred in bit position 7 (15 and 7) or bit position 0 (8 and 0). |
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