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MAX3624UTJ+ Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX3624UTJ+ Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 13 page Low-Jitter, Precision Clock Generator with Four Outputs 8 _______________________________________________________________________________________ Output Divider Configuration Table 2 shows the input settings required to set the out- put dividers. Leakage in the OPEN case must be less than 1µA. Note that when the MAX3624 is in bypass mode (BYPASS set low), the output dividers are auto- matically set to divide by 1. Table 2. Output Divider Configuration Chart INPUT SELA1/SELB1 SELA0/SELB0 NA/NB DIVIDER 0 0 ÷2* 0 1 ÷3* 1 0 ÷4 1 1 ÷5 1 OPEN ÷6 OPEN 1 ÷8 0 OPEN ÷10 OPEN 0 ÷12 OPEN OPEN ÷1* Table 1. Output Frequency Determination Chart XO OR CMOS INPUT FREQUENCY (MHz) FEEDBACK DIVIDER, M VCO FREQUENCY (MHz) OUTPUT DIVIDER, NA AND NB OUTPUT FREQUENCY (MHz) APPLICATIONS ÷2 312.5 ÷4 156.25 ÷5 125 ÷8 78.125 25 25 625 ÷10 62.5 Ethernet 25.78125 25 644.53125 ÷4 161.132812 10Gbps Ethernet ÷2 312.5 ÷4 156.25 ÷5 125 ÷8 78.125 26.04166 24 625 ÷10 62.5 Ethernet ÷2 318.75 ÷3 212.5 ÷4 159.375 ÷6 106.25 26.5625 24 637.5 ÷12 53.125 Fibre Channel ÷2 311.04 ÷4 155.52 19.44 32 622.08 ÷8 77.76 SONET/SDH ÷2 311.04 ÷4 155.52 38.88 (CMOS input) 16 622.08 ÷8 77.76 SONET/SDH *Maximum guaranteed output frequency is 160MHz for CMOS and 320MHz for LVPECL output. |
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