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MAX5590BEUG Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX5590BEUG Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 33 page Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs _______________________________________________________________________________________ 9 TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (DVDD = 1.8V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Frequency fSCLK 1.8V < DVDD < 5.25V 10 MHz SCLK Pulse-Width High tCH (Note 7) 40 ns SCLK Pulse-Width Low tCL (Note 7) 40 ns CS Fall to SCLK Fall Setup Time tCSS 20 ns DSP Fall to SCLK Fall Setup Time tDSS 20 ns SCLK Fall to CS Rise Hold Time tCSH 0ns SCLK Fall to CS Fall Delay tCS0 10 ns SCLK Fall to DSP Fall Delay tDS0 15 ns DIN to SCLK Fall Setup Time tDS 20 ns DIN to SCLK Fall Hold Time tDH 5ns SCLK Rise to DOUT_ Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode 60 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 20 ns CS Pulse-Width High tCSW 90 ns DSP Pulse-Width High tDSW 40 ns DSP Pulse-Width Low tDSPWL (Note 8) 40 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 200 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 40 ns DOUTRB Tri-State Enable Time from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state 40 ns LDAC Pulse-Width Low tLDL Figure 5 40 ns LDAC Effective Delay tLDS Figure 6 200 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 40 ns GPO Output Settling Time tGP Figure 6 200 ns GPO Output High-Impedance Time tGPZ 200 ns Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol- lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation. |
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