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MAX9234EUM Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX9234EUM Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 15 page Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers _______________________________________________________________________________________ 9 MAX9234/MAX9236/MAX9238 vs. MAX9210/MAX9220/MAX9222 The MAX9234/MAX9236/MAX9238 operate in DC-bal- ance mode only. Pinouts are the same as the MAX9210/MAX9220/MAX9222 except that pin 6 on the MAX9234/MAX9236/MAX9238 is no connect (N.C.). DC balance allows AC-coupling with series capacitors. The MAX9234/MAX9236/MAX9238 are hot-swappable and the input frequency can be changed on the fly, but oth- erwise the specifications and functionality are the same as the MAX9210/MAX9220/MAX9222 operating in DC- balance mode. See Table 1. Applications Information Selection of AC-Coupling Capacitors Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capac- itors (C). The RC time constant for two equal-value series capacitors is (C x (RT + RO)) / 2 (Figure 10). The RC time constant for four equal-value series capacitors is (C x (RT + RO)) / 4 (Figure 11). RT is required to match the transmission line imped- ance (usually 100 Ω) and RO is determined by the LVDS driver design (the minimum differential output resis- tance of 78 Ω for the MAX9209/MAX9211/MAX9213/ MAX9215 serializers is used in the following example). This leaves the capacitor selection to change the sys- tem time constant. TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER. DCA0 DCB1 DCA1 DCB2 DCA2 CYCLE N + 1 CYCLE N CYCLE N - 1 TxIN2 TxIN6 TxIN3 TxIN4 TxIN5 TxIN9 TxIN13 TxIN10 TxIN11 TxIN12 TxIN2 TxIN3 TxIN4 DCA0 TxIN5 TxIN6 DCB0 TxIN9 TxIN10 TxIN11 DCA1 TxIN12 TxIN13 DCB1 TxIN16 TxIN17 TxIN18 DCA2 TxIN19 TxIN20 DCB2 TxIN0 TxIN1 TxIN7 TxIN8 TxIN14 TxIN15 TxIN16 TxIN20 TxIN17 TxIN18 TxIN19 DCB0 RxCLK IN RxIN1 RxIN0 RxIN2 TxIN1 TxIN8 TxIN15 TxIN0 TxIN7 TxIN14 + - Figure 9. Deserializer Serial Input 0.8V PWRDWN RxCLK IN RxOUT_ RxCLK OUT RPDD HIGH-Z Figure 8. Power-Down Delay |
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