K7S3236T4C

K7S3218T4C

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Rev. 1.2 March 2007

The K7S3236T4C and K7S3218T4C are37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are

organized as 1,048,576 words by 36bits for K7S3236T4C and 2,097,152 words by 18 bits for K7S3218T4C.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the

same cycle. Memory bandwidth is maximized as data can be transferred into and out of SRAM on every rising edge of K and K. And

totally independent read and write ports eliminate the need for high speed bus turn around.

Address for read and write are latched on alternate rising edges of the input clock K. Data inputs, data output, and all control signals

are synchronized to the input clock ( K or K ). Read data are referenced to echo clock ( CQ or CQ ) outputs. Common address bus is

used to access address both for read and write operations. The internal burst counter is fixed to 4-bit sequential for both read and

write operations, requiring two full clock bus cycles. Any request that attempts to interrupt a burst operation in progress is ignored.

Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished by using R and W

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7S3236T4C and K7S3218T4C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in

165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K. Address is presented and stored in the read

address register synchronized with K clock. For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each

read command.

The first pipelined data is transferred out of the device triggered by K clock rising edge. Next burst data is triggered by the rising edge

of following K clock rising edge. The process continues until all four data are transferred. Continuous read operations are initiated

with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both K and K clocks. Initial read data

latency is 2 clock cycles when DLL is on.

When the R is disabled after a read operation,the K7S3236T4C and K7S3218T4C will first complete burst read operation before

entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating W at the rising edge of the positive input clock K. Address is presented and stored in the write

address register synchronized with K clock. For 4-bit burst DDR operation, it will write four 36-bit or 18-bit data words with each write

command.

The first "late" data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is trans-

ferred and registered synchronous with following K clock rising edge. The process continues until all four data are transferred and

registered. Continuous write operations are initiated with K rising edge. And "late writed" data is presented to the device on every ris-

ing edge of both K and K clocks.

The device disregards input data presented on the same cycle W disabled. When the W is disabled after a write operation, the

K7S3236T4C and K7S3218T4C will first complete burst write operation before entering into deselect mode at the next K clock rising

edge.

Write Operations