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M392T5160CJA-CF7 Datasheet(PDF) 5 Page - Samsung semiconductor |
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M392T5160CJA-CF7 Datasheet(HTML) 5 Page - Samsung semiconductor |
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5 / 26 page  Rev. 1.4 November 2007 RDIMM DDR2 SDRAM 5 of 26 NC = No Connect, RFU = Reserved for Future Use 1. RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5/DQS14 2VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC/DQS14 3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS 4DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46 5VSS 125 DM0/DQS9 35 VSS 155 DM3/DQS12 KEY 95 DQ42 215 DQ47 6DQS0 126 NC/DQS936 DQS3 156 NC/DQS12 65 VSS 185 CK0 96 DQ43 216 VSS 7DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK097 VSS 217 DQ52 8VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC/Par_In 188 A0 99 DQ49 219 VSS 10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 S2 11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 S3 12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC(TEST) 222 VSS 13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6/DQS15 14 VSS 134 DM1/DQS10 44 VSS 164 DM8/DQS17 73 WE 193 S0104 DQS6 224 NC/DQS15 15 DQS1 135 NC/DQS10 45 DQS8 165 NC/DQS17 74 CAS 194 VDDQ 105DQS6225 VSS 16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54 17 VSS 137 RFU 47 VSS 167 CB6 76 S1 196 A13 107 DQ50 227 DQ55 18 RESET 138 RFU 48 CB2 168 CB7 77 ODT1 197 VDD 108DQ51228 VSS 19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60 20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61 21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS 22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7/DQS16 23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4/DQS13 113 DQS7 233 NC/DQS16 24 DQ16 144 DQ21 54 BA2 174 NC 83 DQS4 203 NC/DQS13 114 DQS7 234 VSS 25 DQ17 145 VSS 55 NC/Err_Out 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62 26 VSS 146 DM2/DQS11 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC/DQS11 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS 28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD 29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 VSS * The VDD and VDDQ pins are tied to the single power-plane on PCB. Pin Name Description Pin Name Description CK0 Clock Inputs, positive line ODT0~ODT1 On die termination CK0 Clock inputs, negative line DQ0~DQ63 Data Input/Output CKE0, CKE1 Clock Enables CB0~CB7 Data check bits Input/Output RAS Row Address Strobe DQS0~DQS8 Data strobes CAS Column Address Strobe DQS0~DQS8 Data strobes, negative line WE Write Enable DM(0~8), DQS(9~17) Data Masks / Data strobes (Read) S0~ S3Chip Selects DQS9~DQS17 Data strobes (Read), negative line A0~A9, A11~A13 Address Inputs RFU Reserved for Future Use A10/AP Address Input/Autoprecharge NC No Connect BA0~BA2 DDR2 SDRAM Bank Address TEST Memory bus test tool (Not Connect and Not Useable on DIMMs) SCL Serial Presence Detect (SPD) Clock Input VDD Core Power SDA SPD Data Input/Output VDDQ I/O Power SA0~SA2 SPD address VSS Ground Par_In Parity bit for the Address and Control bus VREF Input/Output Reference Err_Out Parity error found in the Address and Control bus VDDSPD SPD Power RESET Register and PLL control pin 5.0Pin Description 4.0 Pin Configurations (Front side/Back side) |
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