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ES6128F Datasheet(PDF) 3 Page - ESS Technology,Inc |
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ES6128F Datasheet(HTML) 3 Page - ESS Technology,Inc |
3 / 10 page ESS Technology, Inc. SAM0481B-052705 3 ES6128 PRODUCT BRIEF ES6128 PIN DESCRIPTION ES6128 PIN DESCRIPTION Table 1 lists the pin descriptions for the ES6128. Table 1 ES6128 Pin Description Name Pin Numbers I/O Definition VEE 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 P I/O power supply. LA[21:0] 2-7, 10-16, 19-23, 204-207 O RISC port address bus. VSS 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 G Ground. VCC 9, 35, 44, 83, 121, 139, 172 P Core power supply. RESET# 24 I Reset input; (5V tolerant input). TDMDX 25 O TDM transmit data output. RSEL I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k Ω resistor; read only during reset. TDMDR 28 I TDM receive data input; (5V tolerant input). TDMCLK 29 I TDM clock input; (5V tolerant input). TDMFS 30 I TDM frame sync input; (5V tolerant input). TDMTSC# 31 O TDM output enable. TWS 32 O Audio transmit frame sync output. SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-k Ω resistor; read only during reset. TSD0 33 O Audio transmit serial data output 0. SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32. RSEL Selection 016-bit ROM 18-bit ROM SEL_PLL2 SEL_PLL1 SEL_PLL0 PLL Settings 0 0 0 DCLK × 4.5 0 0 1 DCLK × 5.0 01 0 Bypass 0 1 1 DCLK × 4.0 1 0 0 DCLK × 4.25 1 0 1 DCLK × 4.75 1 1 0 DCLK × 5.5 1 1 1 DCLK × 6.0 |
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