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AN256 Datasheet(PDF) 2 Page - Silicon Laboratories |
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AN256 Datasheet(HTML) 2 Page - Silicon Laboratories |
2 / 8 page AN256 2 Rev. 0.2 3.1. Example without Spurs Figure 1 shows a traditional phase noise plot for a 1066 MHz carrier for which we can calculate the integrated jitter. Figure 2 shows the actual timing jitter versus frequency by employing the result of the appendix. This figure also provides a better visual representation of the dominant noise source across the frequency band. Figure 3 expands the first 10 MHz of the plot; the first pass of the rectangular approximation is also shown. Figure 1. Traditional Log-Log Phase Noise Plot Figure 2. Linear-Linear Phase Noise Plot Traditional Log-Log Phase Noise Plot for a 1066MHz Carrier -160 -140 -120 -100 -80 -60 -40 10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6 Offset Frequency (Hz) Linear-Linear Phase Noise Plot for a 1066MHz Carrier 1E-17 1E-16 1E-15 10.0E+0 10.0E+6 20.0E+6 30.0E+6 40.0E+6 50.0E+6 60.0E+6 70.0E+6 80.0E+6 90.0E+6 100.0E+6 Offset Frequency (Hz) |
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