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MAX3341EEUD Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX3341EEUD Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 15 page occurs with handling and assembly during manufactur- ing. All pins require this protection during manufactur- ing. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Applications Information External Components External Resistors Two external 23.7 Ω ±1%, 1/2W resistors are required for USB connection. Place the resistors in between the MAX3341E and the USB connector on the D+ and D- lines. See Typical Operating Circuit. External Capacitors Use three external capacitors for proper operation. Use a 0.1µF ceramic for decoupling VL, a 1µF ceramic for decoupling VCC, and a 1.0µF (min) ceramic or plastic filter capacitor on VTRM. Return all capacitors to GND. UCSP Reliability The UCSP represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. CSP reli- ability is integrally linked to the user’s assembly meth- ods, circuit board material, and usage environment. The user should closely review these areas when con- sidering use of a CSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater considera- tion for a CSP package. CSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be consid- ered. Table 2 shows the testing done to characterize the CSP reliability performance. In conclusion, the UCSP is capable of performing reliably through envi- ronmental stresses as indicated by the results in Table 2. Additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. ±15kV ESD-Protected USB Level Translator in UCSP with USB Detect 10 ______________________________________________________________________________________ D+/D- tPDZ tPZD VOHD - 0.3V VOLD + 0.3V VL 0 VL/2 OE Figure 2. Enable and Disable Timing, Transmitter VPO D+/D- tPHLO VL 0 0.8V 2V VL/2 Figure 3. Mode 0 Timing VPO/VMO D+/D- tPLH1 tPHL1 VL 0 0.8V 2V VL/2 Figure 4. Mode 1 Timing |
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