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SM5816AF Datasheet(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM5816AF Datasheet(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 27 page SM5816AF SEIKO NPC CORPORATION —8 DSD input/output I DSBCKF, DSBCKB pins I DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins I DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins Note. The DSD clock pulsewidth and clock pulse cycle are with both DSBCKF and DSBCKB in input mode. Note. Data is read internally using the falling edge of MCK, using the DSBCKF timing above as the base. When the timing changes, resynchronization must be performed using INIT or SYNC. Parameter Symbol Rating Unit min typ max DSD clock pulsewidth tDSCW 150 177.16 – ns DSD clock pulse cycle tDSCY 300 354.31 (1/64fs) – ns DSD data setup time tDSS 50 – – ns DSD data hold time tDSH 50 – – ns DSD data delay time tDSDLY 0 – 15 ns DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins DSO**: DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins DSBCKF tDSCW tDSCW tDSCY tDSS tDSH DSI** DSBCKB tDSCW tDSCW tDSCY tDSDLY DSO** |
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