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MPC7410VS450NE Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MPC7410VS450NE Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 8 page MPC7410 RISC Microprocessor Hardware Specifications Addendum for the MPC7410xxnnnNE Series, Rev. 2.0 Freescale Semiconductor 3 Features Table 3 provides the recommended operating conditions for the MPC7410 part numbers described herein. Table 2. Input Threshold Voltage Setting BVSEL Signal 3 Processor Bus Input Threshold is Relative to: L2VSEL Signal 3 L2 Bus Input Threshold is Relative to: Note 0 1.8 V 0 1.8 V 1 HRESET 2.5 V HRESET 2.5 V 1, 2 1 Not Supported 1 2.5 V 1, 4, 5 HRESET Not Supported HRESET Not Supported — Notes: 1. Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied. 2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode of operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 ohms should be used. 4. Default voltage setting if left unconnected (internal pulled-up). 5. Caution: The XPC7410RXnnnNE does not support the default OVdd setting of 3.3 V. The BVSEL input must be tie either low or to HRESET. Table 3. Recommended Operating Conditions Characteristic Symbol Recommended Value Unit Core supply voltage Vdd 1.5V ± 50mV V PLL supply voltage AVdd 1.5V ± 50mV V L2 DLL supply voltage L2AVdd 1.5V ± 50mV V Processor bus supply voltage BVSEL = 0 OVdd 1.8V ± 100mV V BVSEL = HRESET OVdd 2.5V ± 100mV V BVSEL = HRESET or BVSEL = 1 OVdd Not Supported V L2 bus supply voltage L2VSEL = 0 L2OVdd 1.8V ± 100mV V L2VSEL = HRESET or L2VSEL = 1 L2OVdd 2.5V ± 100mV V Input voltage Processor bus and JTAG Signals Vin GND to OVdd V L2 Bus Vin GND to L2OVdd V Die-junction temperature Tj 0 to 105 °C Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. |
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