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TMS320DM6435 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320DM6435 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 252 page  www.ti.com TMS320DM6435 Digital Media Processor SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007 SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 5.3 Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted): Updated/Changed table note from "Measured under the following conditions..." to "Assumes the following conditions..." Deleted "VI = VSS to DVDD33 without internal pullup resistor" from Input current [DC] (except I2C) row Updated/Changed IOZ VO = DVDD33 or VSS; internal pull disabled MAX value from "±20 µA" to "±50 µA" Updated/Changed IOH CLK_OUT0/PWM2/GPIO[84] MAX value from "8mA" to "-8mA" Updated/Changed IOH All other peripherals MAX value from "4mA" to "-4mA" Updated/Changed ICDD CVDD = 1.2V, DSP clock = 600 MHz supply current from "TBD" to "524 mA" Updated/Changed ICDD CVDD = 1.2V, DSP clock = 500 MHz supply current from "TBD" to "460 mA" Updated/Changed ICDD CVDD = 1.2V, DSP clock = 400 MHz supply current from "TBD" to "392 mA" Updated/Changed ICDD CVDD = 1.05V, DSP clock = 400MHz supply current from "TBD" to "341 mA" Updated/Changed IDDD 3.3 V I/O DSP clock = 600 MHz supply current from "TBD" to "13 mA" Updated/Changed IDDD 3.3 V I/O DSP clock = 500 MHz supply current from "TBD" to "13 mA" Updated/Changed IDDD 3.3 V I/O DSP clock = 400 MHz supply current from "TBD" to "13 mA" Updated/Changed IDDD 1.8V I/O, CVDD = 1.2 V, DSP clock = 600 MHz supply current from "TBD" to "93 mA" Updated/Changed IDDD 1.8V I/O, CVDD = 1.2 V, DSP clock = 500 MHz supply current from "TBD" to "92 mA" Updated/Changed IDDD 1.8V I/O, CVDD = 1.2 V, DSP clock = 400 MHz supply current from "TBD" to "91 mA" Updated/Changed IDDD 1.8V I/O, CVDD = 1.05 V, DSP clock = 400 MHz supply current from "TBD" to "72 mA" Section 6.5.2 Section 6.5.2, Warm Reset (RESET Pin): Updated/Changed step 4 from "The POR pin may now be deasserted" to "The RESET pin may now be deasserted" Updated/Changed step 4 from "When the POR pin is deasserted" to "When the RESET pin is deasserted" Section 6.5.6 Section 6.5.6, Reset Priority: Updated/Changed first paragraph from "The rest request priorities..." to "The reset request priorities..." Section 6.5.7 Section 6.5.7, Reset Controller Register: Added TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978) reference to paragraph Section 6.6.1 Section 6.6.1, Clock Input Option 1—Crystal Table 6-13, Input Requirements for Crystal: Updated/Changed Frequency stability MAX value from " ± 50 or ± 200" to "± 50" Updated/Changed table note Section 6.7.1 Section 6.7.1, PLL1 and PLL2: Table 6-15, PLLC1 Clock Frequency Ranges: Added "-6 devices at 1.05-V CVDD" and "400 MHz" MAX value to SYSCLK1 (CLKDIV1 Domain) row Updated/Changed PLLOUT MIN values from "400 MHz" to "300 MHz" Section 6.7.4 Section 6.7.4, Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 6-19, Timing Requirements for MXI/CLKIN (-4 -4Q,-4S,-5,-5Q,-5S,-6) Devices: Added "Frequency Stability" Added table note Section 6.4.2 Table 6-7, DM6435 EDMA Registers: Updated/Changed the following registers to "Reserved": QRAE2, QRAE3, DRAE2, DRAEH2, DRAE3, and DRAEH3 Section 6.8 Section 6.8, Interrupts: Deleted "NMI" from "Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts" sentence Added "The NMI input to the C64x+ DSP interrupt controller is not connected internally; therefore, the NMI interrupt is not available." Section 6.9.3 Section 6.9.3, EMIFA Electrical Data/Timing Table 6-24, Timing Requirements for Asynchronous Memory Cycles for EMIFA Module: Added "NOM" column to represent nominal values Updated/Changed tsu(EMDV-EMOEH) MIN value from "TBD" to "5 ns" Updated/Changed tsu(EMOEH-EMDIV) MIN value from "TBD" to "0 ns" Updated/Changed tsu(EMWAIT-EMOEH) MIN value from "4E + TBD" to "4E + 5 ns" Updated/Changed tsu(EMWAIT-EMWEH) MIN value from "4E + TBD" to "4E + 5 ns" Table 6-25, Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module: Added "NOM" column to represent nominal values Added "When EW = 1, the EMIF will extend the strobe period up to 4,096 cycles..." table note Deleted "EW = 1" from tc(EMRCYCLE), tw(EMOEL), tc(EMWCYCLE), and tw(EMWEL) Submit Documentation Feedback Revision History 7 |
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