10/19

●

Command

○

Read Cycle

During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and

Current Read Cycle. The Random Read Cycle reads the data in the indicated address.

The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the

Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the

Sequential Read Cycle it is possible to continuously read the next data.

・

Random Read operation allows the Master to access any memory location indicated by word address.

・

In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal

address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the

next word address (n+1).

・

If an Acknowledge is detected and no STOP condition is generated by the Master (μ-COM), the device will continue to

transmit data. (It can transmit all data (2kbit 256word))

・

If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition

before returning to standby mode.

・

If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and

the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input

Acknowledge with "High" always, then input a STOP condition.

It is necessary to input

“High” at last ACK timing.

A1

A2

D7

11

00

R

E

A

D

S

T

A

R

T

R

/

W

S

T

O

P

DATA

SDA

LINE

SLAVE

ADDRESS

A0

D0

A

C

K

A

C

K

Fig.36 Current Read Cycle Timing

It is necessary to input

“High” at last ACK timing.

Fig.37

Sequential Read Cycle Timing （With Current Read）

Fig.35 Random Read Cycle Timing

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WO R D

ADD R ESS(n)

SDA

LIN E

A

C

K

A

C

K

DATA(n)

A

C

K

SLAV E

ADDRESS

10

0

1A 0

A1

A2

WA

7

A0

D 0

SLAV E

ADDRESS

10

0

1A 1

A2

S

T

A

R

T

D7

R

/

W

R

E

A

D

WA

0

R

E

A

D

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

DATA (n)

SD A

LIN E

A

C

K

A

C

K

DATA (n+x)

A

C

K

SLA V E

ADDRES S

10

0

1A 0

A1

A2

D 0

D7

D 0

D7

It is necessary to

input “High” at

last ACK timing.