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SDA

(IN)

SCL

SDA

(OUT)

SDA

SCL

START BIT

STOP BIT

SDA

SCL

D0

ACK

STOP

CONDITION

START

CONDITION

WRITE DATA(n)

Fig.1-(a) Synchronous Data Timing

Fig.1-(b) Start/Stop Bit Timing

Fig.1-(c) Write Cycle Timing

○

SDA data is latched into the chip at the rising edge

○

of SCL clock.

○

Output data toggles at the falling edge of SCL clock.

Fig.1-(d) WP Timing Of The Write Operation

SCL

WP

SCL

WP

Fig.1-(e) WP Timing Of The Write Cancel Operation

○

For WRITE operation, WP must be "Low" from the rising edge of

the clock (which takes in D0 of first byte) until the end of tWR.

(See Fig.1-(d) ) During this period, WRITE operation can be

canceled by setting WP "High".（See Fig.1-(e)）

○

When WP is set to "High" during tWR, WRITE operation is

immediately ceased, making the data unreliable. It must then

be re-written.

●

FAST-MODE

STANDARD-MODE

Parameter

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Clock Frequency

fSCL

－

－

400

－

－

100

kHz

Data Clock High Period

tHIGH

0.6

－

－

4.0

－

－

μ

s

Data Clock Low Period

tLOW

1.2

－

－

4.7

－

－

μ

s

SDA and SCL Rise Time *1

tR

－

－

0.3

－

－

1.0

μ

s

SDA and SCL Fall Time *1

tF

－

－

0.3

－

－

0.3

μ

s

Start Condition Hold Time

tHD:STA

0.6

－

－

4.0

－

－

μ

s

Start Condition Setup Time

tSU:STA

0.6

－

－

4.7

－

－

μ

s

Input Data Hold Time

tHD:DAT

0

－

－

0

－

－

ns

Input Data Setup Time

tSU:DAT

100

－

－

250

－

－

ns

Output Data Delay Time

tPD

0.1

－

0.9

0.1

－

3.5

μ

s

Output Data Hold Time

tDH

0.1

－

－

0.1

－

－

μ

s

Stop Condition Setup Time

tSU:STO

0.6

－

－

4.0

－

－

μ

s

Bus Free Time

tBUF

1.2

－

－

4.7

－

－

μ

s

Write Cycle Time

tWR

－

－

5

－

－

5

ms

Noise Spike Width (SDA

and SCL)

tI

－

－

0.1

－

－

0.1

μ

s

WP Hold Time

tHD：WP

0

－

－

0

－

－

ns

WP Setup Time

tSU：WP

0.1

－

－

0.1

－

－

μ

s

WP High Period

tHIGH：WP

1.0

－

－

1.0

－

－

μ

s

*1：Not 100％ TESTED

■

Fast / Standard Modes

Fast mode and Standard mode differ only in operation frequency. Operations performed at 100kHz are considered in

"Standard-mode", while those conducted at 400kHz are in "Fast-mode".

Please note that these clock frequencies are maximum values. At lower power supply voltage it is difficult to operate at high

speeds.

The EEPROM can operate at 400kHz, between 2.5V and 3.6V, and at 100kHz from 1.7V-2.5V.

●

Synchronous Data Timing

ｔHIGH : WP

SDA

DATA(n)

WP

STOP BIT

D1

D0

ACK

ACK

DATA(1)

DATA(n)

SDA

D0

ACK

ACK

D1

DATA(1)