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TMP91FW60DFG Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TMP91FW60DFG Datasheet(HTML) 4 Page - Toshiba Semiconductor |
4 / 322 page Date Revision 2007/2/16 1.6 1.1 Features Program patch logic 2.3.4 Prescaler Clock Controller is corrected. 16.Table of SFR's 2.1 RESET 10 system clocks 16us -> 1us 18. Points to Note and Restriction 2007/4/16 1.7 15.2 DC Electrical Characteristics Power down voltage Min 4.5V -> 2.0V 14.6.10 Addresses of Program example are corrected 2007/8/27 1.8 DMAR register (89H) is corrected by RWM prohibition. 18.2 Points of note j. Releasing the HALT mode by requesting an interruption is deleted. 2.3.2 Note3 is added 8.2.1 SIO Plescaler is corrected, and Table 8-2 is corrected 8.3 Note2 and Note3 are added 18.2 Points of note j.Clocks for serial channels (SIO) is added 2007/10/15 1.9 7.3 SFR 16. Table of SFR's TB0FFCR, TB1FFCR, TB2FFCR, TB3FFCR and TB4FFCR register is corrected. |
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