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TMP91FY42FG Datasheet(PDF) 10 Page - Toshiba Semiconductor |
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TMP91FY42FG Datasheet(HTML) 10 Page - Toshiba Semiconductor |
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10 / 332 page  TMP91FY42 91FY42-8 2006-11-08 3. Operation This following describes block by block the functions and operation of the TMP91FY42. Notes and restrictions for eatch book are outlined in 7 “Points of Note and Restrictions” at the end of this manual. 3.1 CPU The TMP91FY42 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For CPU operation, see the “TLCS-900/L1 CPU”. The following describe the unique function of the CPU used in the TMP91FY42; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91FY42 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level for at least 10 system clocks (12 μs at 27MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When the reset is accept, the CPU: • Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> ← Value at FFFF00H address PC<15:8> ← Value at FFFF01H address PC<23:16> ← Value at FFFF02H address • Sets the stack pointer (XSP) to 100H. • Sets bits <IFF2:0> of the status register (SR) to 111 (Sets the interrupt level mark register to level 7). • Sets the <MAX> bit of the status register to 1 (MAX mode). (Note: As this product does not support MIN mode, do not write a 0 to the <MAX>.) • Clears bits <RFP2:0> of the status register to 000 (Sets the register bank to 0). When reset is released,the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. • Initializes the internal I/O registers. • Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. • Sets ALE pin to “High-Z" Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not change by resetting. Figure 3.1.1 is a reset timing of the TMP91FY42. |
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