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TMP93CW46A Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TMP93CW46A Datasheet(HTML) 11 Page - Toshiba Semiconductor |
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11 / 242 page  TMP93CW46A 2004-02-10 93CW46A-9 3. Operation This section describes the functions and basic operational blocks of the TMP93CW46A devices. See the 7. “Points of Note and Restrictions” for the using notice and restrictions for each block. 3.1 CPU The TMP93CW46A device has a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous chapter.) This section describes CPU functions unique to the TMP93CW46A that are not described in the previous chapter. 3.1.1 Reset When resetting the TMP93CW46A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (16 µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When reset is accepted, the CPU sets as follows: • Program counter (PC) according to reset vector that is stored 8000H to 8002H. PC<7:0> ← Data located at 8000H PC<15:8> ← Data located at 8001H PC<23:16> ← Data located at 8002H Note: The address in which the reset vector is stored depends on the respective derivative products. • Stack pointer (XSP) for system mode to 100H. • Status register <IFF2:0> to 111. (Sets mask register to interrupt level 7.) • Status register <MAX> to 1. (Sets to maximum mode.) • Status register <REP2:0> to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from PC (Reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins are as follows. • Initializes built-in I/O registers as per specifications. • Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode. • Sets WDTOUT pin to “0”. (Resetting enables the watchdog timer.) • Pulls up the CLK pin to 1. • Sets the ALE pin to high impedance (High-Z). Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. Note 2: The CLK pin is pulled up during reset. When the voltage is put down externally, there is possible to cause malfunctions. Figure 3.1.1 shows the reset timing chart of TMP93CW46A. |
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