NMOS linear image sensor

S3921/S3924 series

Figure 2 shows the schematic diagram of the photodiode

active area. This active area has a PN junction consisting of

an N-type diffusion layer formed on a P-type silicon substrate.

A signal charge generated by light input accumulates as a

capacitive charge in this PN junction. The N-type diffusion

layer provides high UV sensitivity but low dark current.

s Driver circuit

A start pulse

φst and 2-phase clock pulses φ1, φ2 are needed

to drive the shift register. These start and clock pulses are

positive going pulses and CMOS logic compatible.

The 2-phase clock pulses

φ1, φ2 can be either completely

separated or complementary. However, both pulses must not

be “High” at the same time.

time - 20” ns or more should be input if the rise and fall times

of

φ1, φ2 are longer than 20 ns. The φ1 and φ2 clock pulses

must be held at “High” at least 200 ns. Since the photodiode

signal is obtained at the rise of each

φ2 pulse, the clock pulse

frequency will equal the video data rate.

The amplitude of start pulse

φst is the same as the φ1 and φ2

pulses. The shift register starts the scanning at the “High”

level of

φst, so the start pulse interval is equal to signal accu-

mulation time. The

φst pulse must be held “High” at least 200

ns and overlap with

φ2 at least for 200 ns. To operate the shift

register correctly,

φ2 must change from the “High” level to the

“Low” level only once during “High” level of

φst. The timing

chart for each pulse is shown in Figure 7.

s End of scan

The end of scan (EOS) signal appears in synchronization

with the

φ2 timing right after the last photodiode is addressed,

and the EOS terminal should be pulled up at 5 V using a 10

k

Ω resistor.

tvd

tpw 1

tpw 2

tf s

tr 1

tf 1

X1

X2

t ov

ts r-2

tf 2

RESET

Vr

(H)

Vr

(L)

td r-2

t ovr

tfr

trr

st

V s (H)

V s (L)

V 1 (H)

V 1 (L)

V 2 (H)

V 2 (L)

1

2

END OF SCAN

ACTIVE VIDEO OUTPUT

tpw s

tr s

st

1

2

RESET

Figure 7 Timing chart for driver circuit

s Signal readout circuit

S3921/S3924 series include a current integration circuit uti-

lizing the video line capacitance and an impedance conver-

sion circuit. This allows signal readout with a simple external

circuit. However, a positive bias must be applied to the video

line because the photodiode anode of NMOS linear image

sensors is at 0 V (Vss). This is done by adding an appropriate

pulse to the reset

φ terminal. The amplitude of the reset pulse

should be equal to

φ1, φ2 and φst.

When the reset pulse is at the high level, the video line is set

at the Reset V voltage. Figure 8 shows the Reset V voltage

margin. A higher clock pulse amplitude allows higher Reset

V voltage and saturation charge. Conversely, if the Reset V

voltage is set at a low level with a higher clock pulse ampli-

tude, the rise and fall times of video output waveform can be

shortened. Setting the Reset V voltage to 2.5 V is recom-

mended when the amplitude of

φ1, φ2, φst and Reset φ is 5 V.

To obtain a stable output, an overlap between the reset pulse

(Reset

φ) and φ2 must be settled. (Reset φ must rise while φ2

is at the high level.) Furthermore, Reset

φ must fall while φ2 is

at the low level.

S3921/S3924 series provide output signals with negative-

going boxcar waveform which include a DC offset of approxi-

mately 1 V when Reset V is 2.5 V. If you want to remove the DC

offset to obtain the positive-going output, the signal readout

circuit and pulse timing shown in Figure 9 are recommended.

In this circuit, Rs must be larger than 10 k

Ω. Also, the gain is

determined by the ratio of Rf to Rs, so choose the Rf value

that suits your application.

Figure 8 Reset V voltage margin

4

0

6

8

10

12

4

567

8

10

CLOCK PULSE AMPLITUDE (V)

2

9

MIN.

RESET

V VOLTAGE RANGE

MAX.

RECOMMENDED

RESET

V VOLTAGE

KMPDC0026EA

KMPDB0047EA