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DFPIC1655X Datasheet(PDF) 5 Page - Digital Core Design |
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DFPIC1655X Datasheet(HTML) 5 Page - Digital Core Design |
5 / 7 page All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ● ● ● ● http://www.DigitalCoreDesign.com http://www.dcd.pl I/O Ports – Block contains DFPIC1655X’s general purpose I/O ports and data direction registers (TRIS). The DFPIC1655X has two 8- bit full bi-directional ports PORT A, PORT B. Read and write accesses to the I/O port are performed via their corresponding SFR’s PORTA, PORTB. The reading instruction al- ways reads the status of Port pins. Writing instructions always write into the Port latches. Each port’s pin has an corresponding bit in TRISA and TRISB registers. When the bit of TRIS register is set this means that the corre- sponding bit of port is configured as an input (output drivers are set into the High Imped- ance). DoCD™ Debug Unit – it’s a real-time hard- ware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non- intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller in- cluding all registers, internal, external, pro- gram memories, all SFRs including user de- fined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD™ system includes three-wire inter- face and complete set of tools to communi- cate and work with core in real time debug- ging. It is built as scalable unit and some fea- tures can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. OPTIO N AL M O DULES There are also available an optional pe- ripherals, not included in presented DFPIC1655X Microcontroller Core. The op- tional peripherals, can be implemented in mi- crocontroller core upon customer request. Full duplex UART SPI – Master and Slave Serial Peripheral Interface PWM – Pulse Width Modulation Timer I2C bus controller – Master / Slave PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route: Device Speed grade Logic Cells Fmax CYCLONE -6 660 99 MHz CYCLONE II -6 663 91 MHz STRATIX -5 661 106 MHz STRATIX II -3 591 122 MHz STRATIX GX -5 661 101 MHz APEX II -7 804 71 MHz APEX20KC -7 739 61 MHz APEX20KE -1 739 56 MHz APEX20K -1 739 50 MHz ACEX1K -1 804 39 MHz FLEX10KE -1 804 38 MHz Core performance in ALTERA® devices IMPROVEMENT Most instruction of DFPIC1655X is exe- cuted within 2 CLK cycles. Except the condi- tional program memory branches in case that the condition of branch instruction is met. The table below shows sample instructions execu- tion times: Mnemonic operands DFPIC1655X (CLK cycles) PIC16C554 (CLK cycles) Impr. ADDWF 2 4 2 ANDWF 2 4 2 RLF 2 4 2 BCF 2 4 2 DECFSZ 2(4)1 4(8)1 2 INCFSZ 2(4)1 4(8)1 2 BTFSC 2(4)1 4(8)1 2 BTFSS 2(4)1 4(8)1 2 CALL 2 8 4 GOTO 2 8 4 RETFIE 2 8 4 RETLW 2 8 4 RETURN 2 8 4 1 number of clock in case that result of operation is 0. |
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