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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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BLOCK DIAGRAM

Figure below shows the DI2CM IP Core block

diagram.

address(1:0)

datai(7:0)

datao(7:0)

rd

cs

we

rst

clk

irq

CPU

Interface

sdai

sdao

scli

sclo

Input

Filter

Output

Register

Shift

Register

Clock

Generator

Output

Register

Input

Filter

Timer

Control

Logic

Clock

Synchronization

Send

Data

Receive

Data

Slave

Address

Control

Register

Status

Register

Arbitration

Logic

Output

Register

sclhs

CPU Interface

– Performs the interface func-

tions between DI2CM internal blocks and mi-

croprocessor. Allows easy connection of the

core to a microprocessor/microcontroller sys-

tem.

Control Logic

– Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

Shift Register

– Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Control Register

– Contains five control bits

transmissions.

Status Register

– Contains seven status bits

DI2CM core.

Clock Generator

– Performs generation of

the serial clock.

Input Filter

– Performs spike filtering.

Clock Synchronization

– Performs clock

synchronization.

Arbitration Logic

– Performs arbitration dur-

ing operations in multi-master systems.

Timer

– Allows operation from a wide range of

the input frequencies. It is programmed by an

user before transmission and can be repro-

grammed to change the SCL frequency.

IMPLEMENTATIO N

Figures below show the typical DI2CM imple-

mentations in system with Standard/Fast and

High-speed devices.

open drain

open drain

sdai

SCL

SDA

sdao

sclo

scli

DI2CM

Slave

device

scl

sda

sclhs

DI2CM implementation in I

Standard/Fast devices only

open drain

open drain

sdai

SCL

SDA

sdao

sclo

scli

DI2CM

Slave

device

scl

sda

sclhs

current-source

pull-up

DI2CM implementation in I

High-speed devices