Electronic Components Datasheet Search |
|
DP80C51 Datasheet(PDF) 1 Page - Digital Core Design |
|
DP80C51 Datasheet(HTML) 1 Page - Digital Core Design |
1 / 10 page All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl D DP P8 80 0C C5 51 1 ● ● ● ● ● ● ● ● ● ● ● ● Pipelined High Performance 8-bit Microcontroller ver 4.01 OVERVIEW DP80C51 is an ultra high performance, speed optimized soft core of a single-chip 8- bit embedded controller dedicated for opera- tion with fast (typically on-chip) and slow (off- chip) memories. The core has been designed with a special concern for performance to power consumption ratio. This ratio is ex- tended by an advanced power management unit PMU. DP80C51 soft core is 100% binary and pin compatible with the industry standard 8051 8-bit microcontroller. There are two con- figurations of the DP80C51: Harward, where external data and program buses are sepa- rated, and von Neumann, with common pro- gram and external data bus. DP80C51 has Pipelined RISC architecture up to 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be ex- ploited to great advantage in low power appli- cations where the core can be clocked over ten times more slower than the original implemen- tation for no performance penalty. DP80C51 is delivered with fully auto- mated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES 100% pin compatible with industry standard 8051 100% software compatible with industry standard 8051 Pipelined RISC architecture enables to execute instructions up to 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up to 256 bytes of internal (on-chip) Data Memory Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory Up to 64K bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed Dedicated signal for Program Memory writes. Interface for additional Special Function Registers |
Similar Part No. - DP80C51 |
|
Similar Description - DP80C51 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |