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BLOCK DIAGRAM

Shift register and Read Data Buffer

– it is a

central element in the SPI system. The sys-

tem is single buffered in the transmit direction

and double buffered in the receive direction.

This fact means new data for transmission

cannot be written to the shifter until the previ-

ous transaction is complete; however, re-

ceived data is transferred into a parallel read

data buffer so the shifter is free to accept a

second serial character. As long as the first

character is read out of the read data buffer

before the next serial character is ready to be

transferred, no overrun condition will occur.

When an SPI transfer occurs, an 8-bit char-

acter is shifted out on data pin while a differ-

ent 8-bit character is simultaneously shifted in

a second data pin. Another way to view this

transfer is that an 8-bit shift register in the

master and another 8-bit shift register in the

slave are connected as a circular 16-bit shift

register. When a transfer occurs, this distrib-

uted shift register is shifted eight bit positions;

thus, the characters in the master and slave

are effectively exchanged.

8-Bit Shift Register

MSB

LSB

SPI Clock

Logic

Divider

÷8 - ÷1024

SPI Ctrl. Reg.

SPI Status Reg.

clk

SPR

CPHA

CPOL

SPI

Controller

mo

so

mi

si

scko

scki

scken

datao(7:0)

ss

SS Ctrl. Reg.

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

datai(7:0)

addr(2:0)

cs

we

rd

TX-FIFO

64

÷ 512

RX-FIFO

64

÷ 512

Read buffer

FIFO Ctrl. Reg.

soen

Receiver FIFO

- The Rx FIFO can be 64

(128, 256, 512) levels deep, it receives data

until the number of bytes in the FIFO equals

the selected interrupt trigger level. At that time

if interrupt is enabled, the DSPI_FIFO

will

issue an interrupt to the CPU. The Rx FIFO

will continue to store bytes until it is full, and

will not accept any next byte. Any more data

entering the Rx shift register will set the Over-

run Error flag.

Transmitter FIFO

- the Tx portion of the

DSPI_FIFO transmits data through SO/MO as

soon as the CPU loads a byte into the Tx

FIFO in Master mode. In Slave mode the

transmission is started after correct edge of

the SCK signal. The DSPI_FIFO will prevent

loads to the Tx FIFO if it currently holds 64

(128, 256, 512) characters (depending on

SFCR(5) bit value and selected FIFO size).

Loading to the Tx FIFO again will be enabled

as soon as the next character is transferred to

the Tx shift register. These capabilities ac-

count for the largely autonomous operation of

the Tx

Control Register

may be read or written at

any time, is used to configure the DSPI_FIFO

System. This register controls the mode of

transmission (Master, Slave), polarity and

phase of SPI Clock and transmission speed.

Status Register

(SPSR) is read only register

contains flags indicating the completion of

transfer or occurrence of system errors. All

flags are set automatically when the corre-

sponding event occur and cleared by software

sequence.

Slave Select Control Register

configures

which slave select output should be driven

while SPI master transfer. Contents of SSCR

register is automatically assigned on SS7O-

SS0O pins when DSPI_FIFO master trans-

mission starts.

SPI Clock Logic

- Software can select any of

four combinations of serial clock (SCK) phase

and polarity using two bits in the SPI control

register (SPCR). The clock polarity is specified

by the CPOL control bit, which selects an ac-

tive high or active low clock and has no sig-

nificant effect on the transfer format. The clock

phase (CPHA) control bit selects one of two

fundamentally different transfer formats. The

clock phase and polarity should be identical

for the master SPI device and the communi-

cating slave device. In some cases, the phase

and polarity are changed between transfers to

allow a master device to communicate with

peripheral slaves having different require-

ments. The flexibility of the SPI system on the