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DSP56321VF220 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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DSP56321VF220 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 84 page  DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 1-1 Signals/Connections 1 The DSP56321 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56321 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. See the DSP56321 Reference Manual for details on these configuration registers. Table 1-1. DSP56321 Functional Signal Groupings Functional Group Number of Signals Power (VCC) 20 Ground (GND) 66 Clock 2 Address bus Port A1 18 Data bus 24 Bus control 10 Interrupt and mode control 6 Host interface (HI08) Port B 2 16 Enhanced synchronous serial interface (ESSI) Ports C and D3 12 Serial communication interface (SCI) Port E 4 3 Timer 3 OnCE/JTAG Port 6 Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. 2. Port B signals are the HI08 port signals multiplexed with the GPIO signals. 3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 4. Port E signals are the SCI port signals multiplexed with the GPIO signals. 5. Eight signal lines are not connected internally. These are designated as no connect (NC) in the package description (see Chapter 3). There are also two reserved lines. |
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