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TMP88CP34NG Datasheet(PDF) 10 Page - Toshiba Semiconductor |
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TMP88CP34NG Datasheet(HTML) 10 Page - Toshiba Semiconductor |
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10 / 215 page  TMP88CS34/CP34 2007-09-12 88CS34-10 Figure 1.4.3 Configuration of Timing Generator CGCR (00030H) “0” “0” DV1CK “0” “0” “0” “0” “0” (Initial value: 0000 0000) DV1CK Selection of input clock to the 1’st stage of the divider. 0: fc/4 1: fc/8 R/W Note 1: fc: high-frequency clock [Hz] *: Don’t care Note 2: The all bits except DV1CK are cleared to “0”. Figure 1.4.4 Divider Control Register FC8CR (00FEEH) D1 D0 Read/Write (Initial value: 0000 0010) D1 D0 FC8OUT 1 0 1/2 fc 0 0 1/1 fc Figure 1.4.5 FC8 Control Register Divider Reset circuit Prescaler fm fc Divider Watchdog Timer Machine cycle counters DV1CK Stand-by controller Timer/ Counters Time Base Timer 0 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S Y B A High-frequency clock fc/2 8 Machine cycles States MK8 MHz fc D1 D0 JITTA FC8OUT |
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