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SN54LVT8996 Datasheet(PDF) 9 Page - Texas Instruments |
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SN54LVT8996 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 41 page SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 select protocol The select protocol is the ASP’s means of receiving (at PTDI) address information from an IEEE Std 1149.1 bus master. It follows the ISDDDDDDDDDDSI sequence described previously. A 10-bit address value is decoded from the received data-one and/or data-zero bit pairs. These bit pairs are interpreted in least-significant-bit-first order (that is, the first data bit pair received is considered to correspond to A0). acknowledge protocol Following the receipt of a complete select-protocol sequence, the protocol result provisionally is set to NO MATCH and the connect status set to OFF. The received address is then compared to that at the ASP address inputs (A9–A0). If these address values match, the ASP immediately (with no delay) responds with an acknowledge protocol transmitted from PTDO. This protocol follows the ISDDDDDDDDDDSI sequence described previously. The transmitted address represents the address of the selected ASP which, by definition, is the same address the ASP received in the select protocol. The 10-bit address value is encoded into data-one and/or data-zero bit pairs. The bit pairs are to be interpreted in least-significant-bit-first order (that is, the first data bit pair transmitted is to be considered to correspond to A0). If the received address does not match that at the A9–A0 inputs, no acknowledge protocol is transmitted and the shadow protocol is considered complete. protocol errors Protocol errors occur when bit pairs are received out of sequence. Some of these sequencing errors can be tolerated and produce protocol result SOFT ERROR – no specific action occurs as a result. Other errors represent cases where the addressing information could be incorrectly received and produce protocol result HARD ERROR – these are characterized by sequences in which at least one bit of address data has been properly transmitted, followed by a sequencing error; when protocol result HARD ERROR occurs, any connection to an ASP is dissolved. Table 1 lists the bit-pair sequences that produce protocol results SOFT ERROR and HARD ERROR. A hard error also results when the primary TAP state changes during select protocol following the proper transmission of at least one bit of address data. Figures 16 and 17 show shadow-protocol timing in case of protocol result HARD ERROR while Figure 18 shows shadow-protocol timing in case of protocol result SOFT ERROR. Table 1. Shadow-Protocol Errors† SOFT ERROR HARD ERROR I(D)I I(D)(S)I I(D)(S)(D)I IS(D)I IS(D)S(D)I I(S)I IS(D)S(D)I IS(D)S(S)I IS(S)(D)I IS(D)S(S)I IS(S)(D)(S)I † A bit-pair token in parentheses represents one or more instances. long address Receipt of an address longer than ten bits produces protocol result HARD ERROR and the ASP assumes OFF status. The sole exceptions are when all data ones are received or all data zeros are received. In these special cases, the global addresses represented by these bit sequences are observed and appropriate action taken. That is, in the case that only data ones (ten or more) are received, the shadow-protocol result is TEST SYNCHRONIZATION (if the primary TAP state is Pause-DR or Pause-IR), and in the case that only data zeros (ten or more) are received, the shadow-protocol result is RESET (see test-synchronization address and reset address). |
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