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TMP86FH47AUG Datasheet(PDF) 10 Page - Toshiba Semiconductor |
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TMP86FH47AUG Datasheet(HTML) 10 Page - Toshiba Semiconductor |
10 / 214 page ii 3.4.2.2 Using data transfer instructions 3.4.3 Interrupt return ........................................................................................................................................ 40 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 Address error detection .......................................................................................................................... 41 3.5.2 Debugging .............................................................................................................................................. 41 3.6 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4. Special Function Register (SFR) 4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. Time Base Timer (TBT) 5.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1.1 Configuration .......................................................................................................................................... 49 5.1.2 Control .................................................................................................................................................... 49 5.1.3 Function .................................................................................................................................................. 50 5.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.1 Configuration .......................................................................................................................................... 51 5.2.2 Control .................................................................................................................................................... 51 6. Watchdog Timer (WDT) 6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2.1 Malfunction Detection Methods Using the Watchdog Timer................................................................... 54 6.2.2 Watchdog Timer Enable ......................................................................................................................... 55 6.2.3 Watchdog Timer Disable ........................................................................................................................ 56 6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 56 6.2.5 Watchdog Timer Reset ........................................................................................................................... 57 6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1 Selection of Address Trap in Internal RAM (ATAS)................................................................................ 58 6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 58 6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 58 6.3.4 Address Trap Reset................................................................................................................................ 59 7. I/O Ports 7.1 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.2 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.3 Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.4 Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.5 Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8. 16-Bit TimerCounter 1 (TC1) 8.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 |
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