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TMP86FM48 Datasheet(PDF) 9 Page - Toshiba Semiconductor |
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TMP86FM48 Datasheet(HTML) 9 Page - Toshiba Semiconductor |
9 / 205 page TMP86FM48 2007-08-24 86FM48-7 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86FM48 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data buffer register) and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FM48 memory address map. The general-purpose registers are not assigned to the RAM address space. Figure 1.1.1 Memory Address Maps 1.2 Program Memory (FLASH) The TMP86FM48 has a 32 K × 8 bits (Address 8000H to FFFFH) of program memory (FLASH). The area of 8000H to 81FFH can be used as a 512 × 8 bits data memory of FLASH. FLASH memory: FLASH memory includes: Program memory (The area of 8000H to 81FFH can be used as data memory.) Vector table BOOT ROM: FLASH writing program RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors) Vector table for interrupts (8 vectors) 0000H 64 bytes 2048 bytes 128 bytes SFR RAM DBR FLASH memory (Program memory) 32176 bytes 32 bytes 32 bytes 003FH 0040H 083FH 1F80H 1FFFH 8000H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes FFB0H 2048 bytes BOOT ROM 3800H 3FFFH 512 bytes 81FFH 8200H FLASH memory (Data memory) |
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