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ADS1282IPWR Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1282IPWR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 42 page www.ti.com Frequency(Hz) 0 -20 -40 -60 -80 -100 -180 1 10 100 100k 1k 10k -120 -140 -160 1HzResolution V =20mV IN DC MODULATOR INPUT IMPEDANCE MODULATOR OVER-RANGE MODULATOR OVER-RANGE DETECTION ADS1282 SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007 The modulator is optimized for input signals within a If the inputs are sufficiently overdriven to drive the 4kHz passband. As Figure 7 shows, the noise modulator to full duty cycle (that is, all 1s, all 0s, shaping of the modulator results in a sharp increase or±110%FSR), the modulator enters a stable in noise above 6kHz. The modulator has a chopped saturated state. The digital output code may clip to input structure that further reduces noise within the +FS or –FS, again depending on the duration. A passband. The noise is moved out of the passband small duration overdrive may not always clip the and appears at the chopping frequency (fCLK/512 = output code. When the input returns to the normal 8kHz). The component at 6.5kHz is the tone range, the modulator requires up to 12 modulator frequency, shifted out of band by a 20mV external clock cycles (fMOD) to exit saturation and return to the input. The frequency of the tone is approximately linear region. The digital filter requires an additional VIN/3 (in kHz). 62 conversions for fully settled data (linear phase FIR). In the extreme case of over-range, either input is overdriven exceeding that either analog supply voltage plus an internal ESD diode drop. The internal ESD diodes begin to conduct and the signal on the input is clipped. If the differential input signal range is not exceeded, the modulator remains in linear operation. If the differential input signal range is exceeded, the modulator is saturated but stable, and outputs all 1s or 0s. When the input overdrive is removed, the diodes recovery quickly and the ADS1282 recovers as normal. Note that the linear input range is ±100mV beyond the analog supply voltages; with input levels above this, use care to limit the input current to 100mA peak transient and 10mA continuous. Figure 7. Modulator Output Spectrum The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The The ADS1282 modulator is inherently stable, and charging of the input sampling capacitor draws a therefore, has predictable recovery behavior that transient current from the PGA output. The average results from an input overdrive condition. The value of the current can be used to calculate an modulator does not exhibit self-resetting behavior, effective input impedance of REFF = 1/(fMOD × CS). which often results in an unstable output data stream. Where: The ADS1282 modulator outputs a 1s density data fMOD = Modulator sample frequency (CLK/4) stream at 90% duty cycle with the positive full-scale CS = Input sampling capacitor (22pF, typ) input signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% The resulting modulator input impedance for CLK = modulation, but below 100% modulation (10% and 4.096MHz is 55k Ω. Note that the modulator input 0% for negative overdrive, respectively), the impedance and the PGA output anti-alias resistors modulator remains stable and continues to output the result in a systematic gain error of –1%. CS can vary 1s density data stream. The digital filter may or may ±20% or more over production lots, affecting the gain not clip the output codes to +FS or –FS, depending error. on the duration of the overdrive. When the input returns to the normal range from a long duration overdrive (worst case), the modulator returns (MFLAG) immediately to the normal range, but the group delay The ADS1282 has a fast-responding over-range of the digital filter delays the return of the conversion detection, indicating when the differential input result to within the linear range (31 readings for linear exceeds approximately 100% over-range. The phase FIR). 31 additional readings (62 total) are threshold tolerance is ±2.5%.The MFLAG output required for completely settled data. asserts high when in an over-range condition. As Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS1282 |
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