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STR755FV0 Datasheet(PDF) 8 Page - STMicroelectronics |
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STR755FV0 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 84 page Introduction STR750Fxx STR751Fxx STR752Fxx STR755Fxx 8/84 periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated. WDG (watchdog timer) The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management. Timebase timer (TB) The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering, or to implement the scheduler of a real-time operating system. Synchronizable standard timers (TIM2:0) The three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). They can work together with the PWM timer via the Timer Link feature for synchronization or event chaining. In reset state, timer Alternate Function I/Os are connected to the same I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices, timer Alternate Function I/Os can be connected, or “remapped”, to other I/O ports as summarized in Table 3 and detailed in Table 6. This remapping is done by the application via a control register. Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is mapped to a DMA channel. Motor control PWM timer (PWM) The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6 channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. It has many features in common with the standard TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel. Table 3. Standard timer alternate function I/Os Standard timer functions Number of alternate function I/Os 100-pin package 64-pin package Default mapping Remapped TIM 0 Input Capture 2 1 2 Output Compare/PWM 2 1 2 TIM 1 Input Capture 2 1 1 Output Compare/PWM 2 1 1 TIM 2 Input Capture 2 2 2 Output Compare/PWM 2 1 2 |
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