TMS28F200BZT, TMS28F200BZB

262144 BY 8-BIT/131072 BY 16-BIT

BOOT-BLOCK FLASH MEMORIES

SMJS200E – JUNE 1994 – REVISED JANUARY 1998

6

POST OFFICE BOX 1443

command definition

Once a specific command code has been entered, the WSM executes an internal algorithm generating the

necessary timing signals to program, erase, and verify data. See Table 2 for the CSM command definitions and

data for each of the bus cycles.

Following the read-algorithm-selection-code command, two read cycles are required to access the

manufacturer-equivalent code and the device-equivalent code. The codes are shown in Table 4 and Table 5.

Table 2. Command Definitions

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

COMMAND

CYCLES

REQUIRED

OPERATION

ADDRESS

CSM

INPUT

OPERATION

ADDRESS

DATA

IN / OUT

Read Operations

Read Array

1

Write

X

FFh

Read

X

Data Out

Read Algorithm-Selection Code

3

Write

X

90h

Read

A0

M/D

Read Status Register

2

Write

X

70h

Read

X

SRB

Clear Status Register

1

Write

X

50h

Program Mode

Program Setup / Program

(byte / word)

2

Write

PA

40h or 10h

Write

PA

PD

Erase Operations

Block-Erase Setup/

Block-Erase Confirm

2

Write

BEA

20h

Write

BEA

D0h

Erase-Suspend/

Erase-Resume

2

Write

X

B0h

Write

X

D0h

Legend:

BEA

Block-erase address. Any address selected within a block selects that block for erasure.

M / D

Manufacturer-equivalent/ device-equivalent code (see Table 4 and Table 5 for these codes).

PA

Address to be programmed

PD

Data to be programmed at PA

SRB

Status-register data byte that can be found on DQ0 – DQ7

X

Don’t care

status register

The status register allows the user to determine whether the state of a program/erase operation is pending or

complete. The status register is monitored by writing a read-status command to the CSM and reading the

resulting status code on I/O pins DQ0 – DQ7. This is valid for operation in either the byte- or word-wide mode.

When writing to the CSM in word-wide mode, the high order I/Os (DQ8 – DQ15) can be set to any valid 2-state

level. When reading the status bits during word-wide read operation, the high order I/Os (DQ8 – DQ15) are set

to 00h internally so the user only needs to interpret the low order I/Os (D0 – DQ7).

After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status-register data

until a new command is issued to the CSM. To return the device to other modes of operation, a new command

must be issued to the CSM.

Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals

updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register

input change during a status-register read. To assure that the status-register output contains updated status

data, E or G must be toggled for each subsequent status read.

The status register provides the internal state of the WSM to the external microprocessor. During periods when

the WSM is active, the status register can be polled to determine the WSM status. Table 3 defines the

status-register bits and their functions.