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TMS28F200BZT70BDBJE Datasheet(PDF) 11 Page - Texas Instruments |
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TMS28F200BZT70BDBJE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 29 page TMS28F200BZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SMJS200E – JUNE 1994 – REVISED JANUARY 1998 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset / deep power-down mode Very low levels of power consumption are attained by using a special pin, RP, to disable internal device circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, an ICC value on the order of 0.2 µA (or 1 µW of power) is achievable. This is important in portable applications where extended battery life is of major concern. A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and/or trec(RPHW) in deep power-down mode is required before data-input to the CSM can be recognized. With RP at ground, the WSM is reset and the status register is cleared, effectively eliminating accidental programming to the array during system-reset. After restoration of power, the device does not recognize any operation command until RP is returned to a VIH- or VHH-level. Should RP go low during a program or erase operation, the device will power down and, therefore, will become nonfunctional. Data being written or erased during the power down is invalid or indeterminate, requiring that the operation be performed again after power restoration. |
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