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TC74HC138AF Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74HC138AF Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 9 page TC74HC138AP/AF/AFN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC138AP,TC74HC138AF,TC74HC138AFN 3-to-8 Line Decoder The TC74HC138A is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( 0 Y - 7 Y ) will go low. When enable input G1 is held low or either 2A G or 2B G is held high, decoding function is inhibited and all outputs go high. G1, 2A G , and 2B G inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 16 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 6 V • Pin and function compatible with 74LS138 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HC138AP TC74HC138AF TC74HC138AFN Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) |
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