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CLKIN

CLKINC

DCLKP

1.2V

Reference

EXTIO

EXTLO

BIASJ

ClockMultiplying

PLL 2x-32x

D0P

D0N

D15P

D15N

DCLKN

SYNCP

SYNCN

IOUTA1

IOUTA2

16bit

DAC

DelayLock

Loop (DLL)

FIFOSyncDisable

x2

16

DLL Control

x2

FIR1

ModeControl

DAC_gain

4

SYNC=’0->1'

(transition)

16

PLL Control

Clock

Distribution

FDAC

FDAC/2

PLL Bypass

2

PLL Enable

16

B

A

13

FIR2

(x2 Bypass)

(x1 Bypass)

TXEnable=’1'

FDAC/4

SW_Sync

2

2

47t 76dBHBF

47t 76dBHBF

SyncDisable

DAC5681Z

SLLS865 – AUGUST 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

2

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