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APC12MK03-9MAJ Datasheet(PDF) 5 Page - Astec America, Inc

Part # APC12MK03-9MAJ
Description  Non-Isolated DC/DC Power Module Tiny SMT Footprint - 1.8V-12V Input, 0.9V to 3.6V Output
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Manufacturer  ASTEC [Astec America, Inc]
Direct Link  http://www.astecinc.com/
Logo ASTEC - Astec America, Inc

APC12MK03-9MAJ Datasheet(HTML) 5 Page - Astec America, Inc

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Technical Reference Notes
APC12 Centauri II
MODEL: APC12 SERIES
SHEET 5 OF 23
JANUARY 6, 2002 REVISION A (PRELIMINARY)
Electrical Specifications (continued)
OUTPUT SPECIFICATIONS (continued)
Parameter
Device
Symbol
Min
Typ
Max
Unit
Dynamic Response:
Slew Rate
Load Change: 50% - 75% IO,max
Peak Deviation Settling Time
to VO,nom
All
All
All
∆IO/∆t
-
-
-
-
-
0.1
5
100
-
10
200
A/µs
%VO
µs
Load Change: 50% - 25% IO,max
Peak Deviation Settling Time
to VO,nom
All
All
-
-
-
-
5
100
10
200
%VO
µs
Output Voltage Overshoot
Passive Resistive Full Load
All
-
-
5
-
%Vo
Note:
3. Ripple specs are specified at 56uF decoupling capacitance for 03 devices and 100uF for 08 devices.
4. This feature is only for module protection and is not intended for customer application. The value is
specified at 25°C ambient air temperature. Operation outside the power-derating curve may result to an
OCP.
5. Pulse train with 90ms period and 1 ms pulse width. Average IOUT equals about zero.
6. Input to Output Turn-on time is defined as the difference between t1 and t2: where t1 is the time when
the input voltage reaches the minimum VIN (VIN = VIN,min) and t2 is the time when the output voltage
reaches its specified range (VO = VO,SET-MIN).
FEATURE SPECIFICATION
Parameter
Device
Symbol
Min
Typ
Max
Unit
Output Voltage Adjustment Range7
-9 opt
-9MA opt
-
-
VO
VO
-
-
3.6
3.6
V
V
Module Parallel Capability
VIN = VIN,min to VIN,max at
IO-TOT = (IO,max)/(60%)
Current Sharing to be within:
-9MA opt
-
40
-
60
%IO-TOT
Power Good8
Open Collector: max sink current
max pull-up voltage
All
All
-
-
-
-
5
6
mA
V
Output Enable9
Open Collector TTL compatible
Module ON: Logic High
Module OFF: Logic Low
Collector Current
All
All
All
4.1
0
-
-
-
-
14
0.8
60
Vdc
Vdc
µA
Note:
7. Single resistor adjustment or single resistor plus a voltage source adjustment. Refer to sheet 9 for
recommendations on how to trim the output voltage.
8. Refer to Figure 6 for the PGood configuration.
9. Refer to Figure 3 for the Output Voltage Enable configuration.


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