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PS12014-A Datasheet(PDF) 6 Page - Powerex Power Semiconductors |
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PS12014-A Datasheet(HTML) 6 Page - Powerex Power Semiconductors |
6 / 6 page MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLAT-BASE TYPE INSULATED TYPE Jan. 2000 UP,VP,WP,UN,VN,WN,Br FO1,FO2,FO3,CL CU,CV,CW GND(Logic) VDL(5V) ASIPM CPU 10k Ω 5.1k Ω 0.1nF R R 0.1nF on on on on 0 0 0 VPN DC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO1 output signal VDB VCIN(N) VCIN(P) VCIN(Br) FOI VDH, DL b) a) PWM starts N-side IGBT Current N-side FWDi Current t(hold) td(read) Delay time +ICL –ICL on off on off 0 0 on off 0 Ref VCIN V(hold) IC (VS) VC VCL Fig. 9 START-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to VDL voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20 µs number of pulses =10 ~ 500 de- pending on the boot-strap capacitor size) b) FO1 resetting sequence: Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order. Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART. |
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