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TA1317AFG Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TA1317AFG Datasheet(HTML) 11 Page - Toshiba Semiconductor |
11 / 58 page TA1317AFG 2005-08-18 11 Register Name/Number of Bits Function Explanation Output Change Picture Change Preset V-EHT COMPENSATION/3 Adjusts the compensated rate for the V-DRIVE by EHT-IN (pin 3). 000: min 111: max min (000) ANALOG V-BLK STOP PHASE/5 Sets the analog blanking stop phase on pin 24. Inputs the output from pin 20 to an external BLK-IN of synchronization IC. 00000: min 10000: center 11111: max ⎯ center (10000) H-EHT COMPENSATION/3 Adjusts the compensated rate for the EW output by EHT-IN (pin 3). 000: min 111: max min (000) ANALOG V-BLK START PHASE/5 Sets the analog blanking start phase on pin 24. Inputs the output from pin 24 to external BLK-IN of synchronization IC. 00000: min 10000: center 11111: max ⎯ center (10000) V-RAMP LIMIT LEVEL/4 Sets the V-ramp slice level. 0000: OFF 0001: min 1111: max Sub-address 05-D0 bit comes MSB. ⎯ OFF (0000) Solid line Dashed line Solid line Dashed line Solid line Dashed line Solid line Dashed line Pin 7 Pin 14 Pin 7 |
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