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MSP430FW423IPM Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430FW423IPM Datasheet(HTML) 9 Page - Texas Instruments |
9 / 54 page MSP430xW42x MIXED SIGNAL MICROCONTROLLER SLAS383B − OCTOBER 2003 − REVISED JUNE 2007 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 7 654 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 00h ACCVIE NMIIE rw-0 7 654 0 32 1 Address 01h BTIE rw-0 WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable BTIE: Basic Timer1 interrupt enable interrupt flag register 1 and 2 7 654 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG 7 654 0 32 1 Address 03h BTIFG rw-0 WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up, or a reset condition at the RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin BTIFG: Basic Timer1 interrupt flag module enable registers 1 and 2 7 654 0 32 1 Address 04h/05h rw-0,1: Legend: rw: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device rw-(0,1): |
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