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TB1305FG Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TB1305FG Datasheet(HTML) 4 Page - Toshiba Semiconductor |
4 / 33 page TB1305FG, TB1308FG 2007-07-11 4 Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 24 26 HD1-IN HD2-IN HD input pin. Input a separated horizontal sync signal (1.0 to 2.0 Vp-p) via a resister and a coupling capacitor. The polarity of the input signal is detected and its leading edge becomes a timing trigger. 23 25 VD1-IN VD2-IN VD input pin. Input a separated vertical sync signal (1.0 to 2.0 Vp-p) via a resister and a coupling capacitor. The polarity of the input signal is detected and its leading edge becomes a timing trigger. 22 200Ω 20 23 24 25 26 1.45 V bias (typ.) or 6 15 LINE1-1 LINE1-2 LINE1 (number of lines) detection pin. Connect LINE1 of D-pin. DC 2 11 LINE3-1 LINE3-2 LINE3 (aspect ratio) detection pin. Connect LINE3 of D-pin. 46 1kΩ 44 Th1 Th2 2 6 11 15 200Ω DC 4 13 LINE2-1 LINE2-2 LINE2 (i/p) detection pin. Connect LINE2 of D-pin. DC 48 9 SW LINE1 SW LINE2 SW LINE detection pin. Connect SW LINE of D-pin. 46 1kΩ 44 4 9 13 48 200Ω DC 32 Y-OUT Y, G or CVBS signal output pin. 34 Cb-OUT Cb, Pb, B or C signal output pin. 36 Cr-OUT Cr, Pr or R signal output pin. 46 44 32 34 36 100Ω AC: 0 dB or +6 dB (typ.) 28 SYNC-OUT Separated composite sync output pin. 0.1V(typ.) 3.4V(typ.) 29 30 VD-OUT HD-OUT HD or VD output pin. The polarity of the output is selectable by HV-POL register. The tailing edge of the VD-OUT has a jitter. Use the leading edge only. 31 33 28 29 30 100Ω 0.1V(typ.) 3.4V(typ.) or 0.1V(typ.) 3.4V(typ.) 17 42 DAC1 DAC2 1-bit DAC output pin. Open-collector pin. 31 33 17 42 100Ω 100Ω DAC TEST DC |
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