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EM78452 Datasheet(PDF) 9 Page - ELAN Microelectronics Corp

Part # EM78452
Description  8-Bit Microcontroller
Download  54 Pages
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Manufacturer  EMC [ELAN Microelectronics Corp]
Direct Link  http://www.emc.com.tw
Logo EMC - ELAN Microelectronics Corp

EM78452 Datasheet(HTML) 9 Page - ELAN Microelectronics Corp

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EM78452
8-Bit Microcontroller
Product Specification (V1.0) 10.18.2007
• 5
(This specification is subject to change without further notice)
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows it to jump to any location on one page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
at the top of the stack.
"MOV R2, A" allows the loading of an address from the "A" register to the lower 8
bits of PC, and the ninth and tenth bits (A8~A9) of the PC are cleared.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",
⋅⋅⋅⋅⋅)
(except "TBL") will cause the ninth and tenth bits (A8~A9) of the PC to be cleared.
Thus, the computed jump is limited to the first 256 locations of any program page.
"TBL" allows a relative address to be added to the current PC (R2+A
→R2), and
contents of the ninth and tenth bits (A8~A9) of the PC are not changed. Thus, the
computed jump can be on the second (or third, 4th) 256th locations on one
program page.
In the case of EM78452, the most significant bits (A10~A11) will be loaded with the
contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP",
"CALL", or any other instructions which writes to R2.
All instructions are single instruction cycle (fclk/2 or fclk/4 except for instructions
that would change the contents of R2. Such instruction will need one more
instruction cycle.
A7
~
A0
On-chip Program
Memory
000H
FFFH
001H
Hardware Vector
Software Vector
Reset Vector
002H
A9 A8
A11 A10
Stack Level 1
Stack Level 3
Stack Level 2
Stack Level 4
Stack Level 5
CALL
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
R3
RET
RETL
RETI
Fig. 5-2 Program Counter Organization


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